ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 54

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ep1agx50d

Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Adaptive Logic Modules
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1)
2–46
Arria GX Device Handbook, Volume 1
If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Figure
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(1)
2–33:
This input is available
for register packing.
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of 2 four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and
datab inputs. As shown in
adder0, and the carry-out from adder0 feeds to carry-in of adder1. The
carry-out from adder1 drives to adder0 of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
5-Input
5-Input
LUT
LUT
combout0
Figure
2–34, the carry-in signal feeds to
D
reg0
Q
To general or
To general or
local routing
local routing
Altera Corporation
May 2008

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