ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 26

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
Figure 2–15. Word Aligner
2–18
Arria GX Device Handbook, Volume 1
complement of a given pattern. Once the programmed pattern is found,
the data stream is aligned to have the pattern on the LSB portion of the
data output bus.
XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have
embedded state machines for symbol boundary synchronization. These
standards use K28.5 as their 10-bit programmed comma pattern. Each of
these standards uses different algorithms before signaling symbol
boundary acquisition to the FPGA.
pattern detection logic searches from the LSB to the most significant bit
(MSB). If multiple patterns are found within the search window, the
pattern in the lower portion of the data stream (corresponding to the
pattern received earlier) is aligned and the rest of the matching patterns
are ignored.
Once a pattern is detected and the data bus is aligned, the word boundary
is locked. The two detection status signals (rx_syncstatus and
rx_patterndetect) indicate that an alignment is complete.
Figure 2–15
Control and Status Signals
The rx_enapatternalign signal is the FPGA control signal that
enables word alignment in non-automatic modes. The
rx_enapatternalign signal is not used in automatic modes (PCI
Express [PIPE], XAUI, GIGE, and Serial RapidIO).
In manual alignment mode, after the rx_enapatternalign signal is
activated, the rx_syncstatus signal goes high for one parallel clock
cycle to indicate that the alignment pattern has been detected and the
word boundary has been locked. If rx_enapatternalign is
datain
bitslip
enapatternalign
clock
is a block diagram of the word aligner.
Aligner
Word
patterndetect
syncstatus
dataout
Altera Corporation
May 2008