ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 190

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Timing Model
4–36
Arria GX Device Handbook, Volume 1
Use the following equations to calculate clock pin to output pin timing for
Arria GX devices:
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
2.
3.
4.
5.
The Quartus II software reports the timing with the conditions shown in
Table 4–44
circuit that is represented by the output timing of the Quartus II software.
t
t
Simulate the output driver of choice into the generalized test setup,
using values from
Record the time to V
Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
CO
xz
/t
from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay
zx
output register + IOE output register clock-to-output delay +
delay from output register to output pin + I/O output delay +
output enable pin delay
using the above equation.
from clock pin to I/O pin = delay from clock pad to I/O
Table
MEAS
MEAS
4–44.
.
.
Figure 4–7
shows the model of the
Altera Corporation
May 2008