ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 58

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Adaptive Logic Modules
Figure 2–36. ALM in Shared Arithmetic Mode
Note to
(1)
2–50
Arria GX Device Handbook, Volume 1
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Figure
datae0
datae1
datab
dataa
datad
datac
2–36:
Adder trees are used in many different applications. For example, the
summation of partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology. An example of a three-bit add operation
utilizing the shared arithmetic mode is shown in
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs,
while the result (R[2..0]) is computed using dedicated adders.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
D
D
reg0
reg1
Q
Q
Figure
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Altera Corporation
2–37. The partial
May 2008