ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 144

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Configuration and Testing
SignalTap II
Embedded Logic
Analyzer
Configuration
3–4
Arria GX Device Handbook, Volume 1
Device
EP1AGX60
EP1AGX90
Table 3–3. 2-Bit Arria GX Device IDCODE (Part 2 of 2)
Version (4 Bits)
0000
0000
Arria GX devices feature the SignalTap II embedded logic analyzer,
which monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
(FBGA) packages, because it can be difficult to add a connection to a pin
during the debugging process after a board is designed and
manufactured.
The logic, circuitry, and interconnects in the Arria GX architecture are
configured with CMOS SRAM elements. Altera
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Arria GX devices are configured at system power up with data stored in
an Altera configuration device or provided by an external controller (for
example, a MAX
Arria GX devices using the fast passive parallel (FPP), active serial (AS),
passive serial (PS), passive parallel asynchronous (PPA), and JTAG
configuration schemes. Each Arria GX device has an optimized interface
that allows microprocessors to configure it serially or in parallel, and
synchronously or asynchronously. The interface also enables
microprocessors to treat Arria GX devices as memory and configure them
by writing to a virtual memory location, making reconfiguration easy.
In addition to the number of configuration methods supported, Arria GX
devices also offer decompression and remote system upgrade features.
The decompression feature allows Arria GX FPGAs to receive a
compressed configuration bitstream and decompress this data in
real-time, reducing storage requirements and configuration time. The
remote system upgrade feature allows real-time system upgrades from
remote locations of Arria GX designs. For more information, refer to
“Configuration Schemes” on page
Part Number (16 Bits)
0010 0001 0010 0010
0010 0001 0010 0011
®
II device or microprocessor). You can configure
IDCODE (32 Bits)
3–6.
Manufacturer
Identity (11 Bits)
000 0110 1110
000 0110 1110
®
FPGAs are
Altera Corporation
LSB (1 Bit)
May 2008
1
1