ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 43

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Logic Array
Blocks
Altera Corporation
May 2008
Region0
8 LRIO clock
Region1
8 LRIO clock
Region2
8 LRIO clock
Region3
8 LRIO clock
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E
Source
Global Clock
v
v
v
v
Clock Resource
Each logic array block (LAB) consists of eight adaptive logic modules
(ALMs), carry chains, shared arithmetic chains, LAB control signals, local
interconnects, and register chain connection lines. The local interconnect
transfers signals between ALMs in the same LAB. Register chain
connections transfer the output of an ALM register to the adjacent ALM
register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
Table 2–9
Arria GX LAB structure.
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
Table 2–9. Arria GX Device Resources
Device
RCLK 20-27
RCLK 20-27
RCLK 12-19
RCLK 12-19
Regional
shows Arria GX device resources.
Clock
Columns/Blocks
M512 RAM
166
197
313
326
478
8 Clock I/O
Bank13
v
v
Columns/Blocks
M4K RAM
Arria GX Device Handbook, Volume 1
118
140
242
252
400
8 Clock I/O
Transceiver
Bank14
v
v
Figure 2–25
M-RAM
Blocks
Arria GX Architecture
1
1
2
2
4
shows the
8 Clock I/O
Bank15
Columns/Blocks
v
v
DSP Block
10
14
26
32
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