ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 107

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–65. Arria GX Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
May 2008
Global or
Regional
Clock
INCLK[3..0]
Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Figure
4
Shaded Portions of the
PLL are Reconfigurable
2–65:
FBIN
Switchover
Circuitry
Clock
(2)
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock
management features. These features include support for external clock
feedback mode, spread-spectrum clocking, and counter cascading.
Figure 2–65
Fast PLLs
Arria GX devices contain up to four fast PLLs with high-speed serial
interfacing ability. Fast PLLs offer high-speed outputs to manage the
high-speed differential I/O interfaces.
the fast PLL.
/n
Phase Frequency
Detector
PFD
Note (1)
shows a diagram of the enhanced PLL.
Charge
Pump
Lock Detect
& Filter
Spectrum
/m
Spread
Loop
Filter
VCO Phase Selection
Affecting All Outputs
V
Selectable at Each
PLL Output Port
CO
Phase Selection
VCO
8
Arria GX Device Handbook, Volume 1
Figure 2–66
Post-Scale
Counters
/c0
/c1
/c2
/c3
/c4
/c5
From Adjacent PLL
6
shows a diagram of
Arria GX Architecture
4
8
6
Global
Clocks
Regional
Clocks
I/O Buffers (3)
to I/O or general
routing
2–99