ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 152

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Configuration and Testing
Automated
Single Event
Upset (SEU)
Detection
Referenced
Documents
3–12
Arria GX Device Handbook, Volume 1
f
Arria GX devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. Some applications that require the device to
operate error free at high elevations or in close proximity to Earth’s North
or South Pole will require periodic checks to ensure continued data
integrity. The error detection cyclic redundancy check (CRC) feature
controlled by the Device and Pin Options dialog box in the Quartus II
software uses a 32-bit CRC circuit to ensure data reliability and is one of
the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Arria GX devices, eliminating the need for external logic. Arria GX
devices compute CRC during configuration. The Arria GX device checks
the computed-CRC against an automatically computed CRC during
normal operation. The CRC_ERROR pin reports a soft error when
configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Arria GX devices to automatically
perform error detection. This circuitry constantly checks for errors in the
configuration SRAM cells while the device is in user mode. You can
monitor one external pin for the error and use it to trigger a
reconfiguration cycle. You can select the desired time between checks by
adjusting a built-in clock divider.
Software Interface
Beginning with version 7.1 of the Quartus II software, you can turn on the
automated error detection CRC feature in the Device and Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the Arria GX FPGA.
For more information about CRC, refer to
CRC in Altera
This chapter references the following documents:
■
■
■
■
AN 357: Error Detection Using CRC in Altera FPGAs
AN414: JRunner Software Driver: An Embedded Solution for PLD JTAG
Configuration
AN418: SRunner: An Embedded Solution for Serial Configuration Device
Programming
AN423: Configuring the MicroBlaster Passive Serial Software Driver
FPGAs.
AN 357: Error Detection Using
Altera Corporation
May 2008