8.10.00 J-TRACE ARM Segger Microcontroller Systems, 8.10.00 J-TRACE ARM Datasheet - Page 158

• Manufacturer Part Number: 8.10.00 J-TRACE ARM
• Description: JTAG EMULATOR ARM7/ARM9 ETM
• Manufacturer: Segger Microcontroller Systems
• Type: Emulatorr

Specifications of 8.10.00 J-TRACE ARM

• Contents: Emulation Module
• For Use With/related Products: ARM7, ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 899-1006

158
7.2.2
7.2.2.1 JTAG settings
J-Link / J-Trace (UM08001)
IAR Sample
/*******************************************************************
*
*
*/
_Init() {
}
/*******************************************************************
*
*
*/
execUserReset() {
}
/*******************************************************************
*
*
*/
execUserPreload() {
}
RDI Sample
SetJTAGSpeed(30);
Reset(0, 0);
Write32(0xFFFFFD00, 0xA5000004);
Write32(0xFFFFFD44, 0x00008000);
Write32(0xFFFFFC20, 0x00000601);
Delay(200);
Write32(0xFFFFFC2C, 0x00191C05);
Delay(200);
Write32(0xFFFFFC30, 0x00000007);
Write32(0xFFFFFF60, 0x00320300);
SetJTAGSpeed(12000);
These devices are based on ARM926EJ-S core. All devices of this family are sup-
ported by J-Link.
We recommend using adaptive clocking.
This information is applicable to the following devices:
•
•
•
•
•
__emulatorSpeed(30000);
__writeMemory32(0xA5000004,0xFFFFFD00,"Memory");
__sleep(20000);
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__sleep(20000);
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
__sleep(20000);
__writeMemory32(0x10191c05,0xFFFFFC2C,"Memory");
__sleep(20000);
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
__sleep(20000);
__writeMemory32(0x002f0100,0xFFFFFF60,"Memory");
__sleep(20000);
__emulatorSpeed(12000000);
__message "execUserReset()";
_Init();
__message "execUserPreload()";
_Init();
AT91RM9200
AT91SAM9260
AT91SAM9261
AT91SAM9262
AT91SAM9263
AT91SAM9
_Init()
execUserReset()
execUserPreload()
CHAPTER 7
// Set JTAG speed to 30 kHz
// Perform peripheral reset
// Disable watchdog
// Set PLL
// Set PLL and divider
// Select master clock and processor clock
// Set flash wait states
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
// Set JTAG speed to 30 kHz
// Perform peripheral reset
// Disable Watchdog
// PLL
// PLL
// PLL
// Set 1 wait state for
// flash (2 cycles)
// Use full JTAG speed
Device specifics