8.10.00 J-TRACE ARM Segger Microcontroller Systems, 8.10.00 J-TRACE ARM Datasheet - Page 140

• Manufacturer Part Number: 8.10.00 J-TRACE ARM
• Description: JTAG EMULATOR ARM7/ARM9 ETM
• Manufacturer: Segger Microcontroller Systems
• Type: Emulatorr

Specifications of 8.10.00 J-TRACE ARM

• Contents: Emulation Module
• For Use With/related Products: ARM7, ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 899-1006

140
5.13 Cache handling
5.13.1 Cache coherency
5.13.2 Cache clean area
5.13.3 Cache handling of ARM7 cores
5.13.4 Cache handling of ARM9 cores
J-Link / J-Trace (UM08001)
Most ARM systems with external memory have at least one cache. Typically, ARM7
systems with external memory come with a unified cache, which is used for both
code and data. Most ARM9 systems with external memory come with separate caches
for the instruction bus (I-Cache) and data bus (D-Cache) due to the hardware archi-
tecture.
When debugging or otherwise working with a system with processor with cache, it is
important to maintain the cache(s) and main memory coherent. This is easy in sys-
tems with a unified cache and becomes increasingly difficult in systems with hard-
ware architecture. A write buffer and a D-Cache configured in write-back mode can
further complicate the problem.
ARM9 chips have no hardware to keep the caches coherent, so that this is the
responsibility of the software.
J-Link / J-Trace handles cache cleaning directly through JTAG commands. Unlike
other emulators, it does not have to download code to the target system. This makes
setting up J-Link / J-Trace easier. Therefore, a cache clean area is not required.
Because ARM7 cores have a unified cache, there is no need to handle the caches dur-
ing debug.
ARM9 cores with cache require J-Link / J-Trace to handle the caches during debug. If
the processor enters debug state with caches enabled, J-Link / J-Trace does the fol-
lowing:
When entering debug state
J-Link / J-Trace performs the following:
•
•
When leaving debug state
J-Link / J-Trace performs the following:
•
•
Note:
However, the cache is handled correctly for all supported ARM9 cores.
it stores the current write behavior for the D-Cache
it selects write-through behavior for the D-Cache.
it restores the stored write behavior for the D-Cache
it invalidates the D-Cache.
The implementation of the cache handling is different for different cores.
CHAPTER 5
© 2004-2011 SEGGER Microcontroller GmbH & Co. KG
Working with J-Link and J-Trace