HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 709

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
12.4
Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
Pulse output pin
Operation
Figure 12.2 Overview Diagram of PPG
DDR
Normal output/inverted output
Section 12 Programmable Pulse Generator (PPG)
Q
NDER
Q
PODR
C
Output trigger signal
Rev.7.00 Mar. 18, 2009 page 641 of 1136
D
Q
NDR
D
Internal data bus
REJ09B0109-0700

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