HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 467

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of dead cycle.
Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level
φ
EDREQ
Address bus
DMA control
Channel
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
Read
Request clearance period
[3]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
Transfer
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
Rev.7.00 Mar. 18, 2009 page 399 of 1136
Section 8 EXDMA Controller (EXDMAC)
[5]
Read
Request clearance period
[6]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
REJ09B0109-0700
Transfer
Idle
Acceptance
resumed
[7]
Bus release