HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 282

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 6 Bus Controller (BSC)
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low
from the T
Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
Rev.7.00 Mar. 18, 2009 page 214 of 1136
REJ09B0109-0700
Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
Read
Write
Note: n = 2 to 5
c1
DACK or EDACK
state.
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
(RAST = 0, CAST = 0)
T
p
Row address
High
High
T
r
T
c1
Column address
T
c2

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