HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 377

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4.2
If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port
should be set to input mode in advance * . Level sensing or edge sensing can be used for external
requests.
External request operation in normal mode of short address mode or full address mode is
described below.
When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is
detected on the DREQ pin. The next data transfer may not be performed if the next edge is input
before data transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Note: * If the relevant port is set as an output pin for another function, DMA transfers using the
7.4.3
Auto-request is activated by register setting only, and transfer continues to the end. With auto-
request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
7.5
7.5.1
Table 7.4 lists the DMAC transfer modes.
Activation by External Request
Activation by Auto-Request
Operation
Transfer Modes
channel in question cannot be guaranteed.
Rev.7.00 Mar. 18, 2009 page 309 of 1136
Section 7 DMA Controller (DMAC)
REJ09B0109-0700