HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 304
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412373R.pdf
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Section 6 Bus Controller (BSC)
TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be
extended by the RCW1 and RCW0 bits after the precharge cycles.
T
T
T
T
T
T
Rp1
Rp2
Rrw
Rr
Rc1
Rc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
REF
NOP
Figure 6.55 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.
Rev.7.00 Mar. 18, 2009 page 236 of 1136
REJ09B0109-0700
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