HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 621

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
0, 3
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
1, 2, 4, 5
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
buffer register setting has priority, and compare match/input capture does not occur.
modified.
Bit 7
CCLR2
0
1
Bit 7
Reserved *
0
2
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture *
TCNT cleared by TGRD compare match/input
capture *
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Rev.7.00 Mar. 18, 2009 page 553 of 1136
Section 11 16-Bit Timer Pulse Unit (TPU)
2
2
1
1
1
REJ09B0109-0700