HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 356

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 7 DMA Controller (DMAC)
Bit
3
2
1
0
Rev.7.00 Mar. 18, 2009 page 288 of 1136
REJ09B0109-0700
Bit Name
DTF3
DTF2
DTF1
DTF0
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
0000: Setting prohibited
0001: Activated by A/D converter conversion end
0010: Activated by DREQ pin falling edge input
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmission
0101: Activated by SCI channel 0 reception
0110: Activated by SCI channel 1 transmission
0111: Activated by SCI channel 1 reception
1000: Activated by TPU channel 0 compare
1001: Activated by TPU channel 1 compare
1010: Activated by TPU channel 2 compare
1011: Activated by TPU channel 3 compare
1100: Activated by TPU channel 4 compare
1101: Activated by TPU channel 5 compare
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than one
channel. In this case, activation starts with the
highest-priority channel according to the relative
channel priorities. For relative channel priorities,
see section 7.5.12, Multi-Channel Operation.
Channel B
interrupt
(detected as a low level in the first transfer
after transfer is enabled)
complete interrupt
complete interrupt
complete interrupt
complete interrupt
match/input capture A interrupt
match/input capture A interrupt
match/input capture A interrupt
match/input capture A interrupt
match/input capture A interrupt
match/input capture A interrupt

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