HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 229
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412373R.pdf
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Bit
2
1
0
Bit Name
MXC2
MXC1
MXC0
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Address Multiplex Select
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM/synchronous DRAM
interface, these bits also select the row address
bits to be used for comparison.
When the MXC2 bit is set to 1 while continuous
synchronous DRAM space is set, the address
precharge setting command (Precharge-sel) is
output to the upper column address. For details,
refer to sections 6.6.2 and 6.7.2, Address
Multiplexing.
DRAM interface
000: 8-bit shift
•
•
001: 9-bit shift
•
•
010: 10-bit shift
•
•
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
Rev.7.00 Mar. 18, 2009 page 161 of 1136
Section 6 Bus Controller (BSC)
REJ09B0109-0700
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