HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 337

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 6 Bus Controller (BSC)
On-chip memory read Internal I/O register read
External write cycle
T
T
T
T
T
1
2
W
W
3
φ
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
External address
A23 to A0
CSn
External space
write
HWR, LWR
D15 to D0
Figure 6.83 Example of Timing when Write Data Buffer Function Is Used
6.11
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC * continue to operate as long
as there is no external access. If any of the following requests are issued in the external bus
released state, the BREQO signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
Note: * Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
Rev.7.00 Mar. 18, 2009 page 269 of 1136
REJ09B0109-0700

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