HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 228
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Section 6 Bus Controller (BSC)
Bit
4
3
Rev.7.00 Mar. 18, 2009 page 160 of 1136
REJ09B0109-0700
Bit Name
EDDS
—
Initial Value
0
0
R/W
R/W
R/W
Description
EXDMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when EXDMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst access,
EXDMAC single address transfer is performed in
full access mode regardless of the setting of this
bit.
This bit has no effect on other bus master external
accesses or EXDMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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