HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 735
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412373R.pdf
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13.5.5
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.8
shows the timing of this operation.
13.5.6
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.9
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
Timing of TCNT External Reset
Timing of Overflow Flag (OVF) Setting
φ
TCNT
Overflow signal
OVF
Figure 13.8 Timing of Clearance by External Reset
Figure 13.9 Timing of OVF Setting
N – 1
H'FF
Rev.7.00 Mar. 18, 2009 page 667 of 1136
N
H'00
Section 13 8-Bit Timers (TMR)
H'00
REJ09B0109-0700
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