HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 415

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Figure 7.33 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.12
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
Multi-Channel Operation
DACK
RD
φ
DMA
read
DMA
single
Full Address Mode
Channel 0
Channel 1
CPU
read
Rev.7.00 Mar. 18, 2009 page 347 of 1136
Section 7 DMA Controller (DMAC)
DMA
single
Priority
High
Low
CPU
read
REJ09B0109-0700

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