HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 625

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.3.2
TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR
registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit
7, 6
5
4
3
2
1
0
Bit Name
—
BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)
Initial Value
All 1
0
0
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together
for buffer operation. When TGRD is used as a
buffer register, TGRD input capture/output compare
is not generated.
In channels 1, 2, 4, and 5, which have no TGRD,
bit 5 is reserved. It is always read as 0 and cannot
be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together
for buffer operation. When TGRC is used as a
buffer register, TGRC input capture/output compare
is not generated.
In channels 1, 2, 4, and 5, which have no TGRC,
bit 4 is reserved. It is always read as 0 and cannot
be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer
Modes 3 to 0
These bits are used to set the timer operating
mode.
MD3 is a reserved bit. The write value should
always be 0. See table 11.11 for details.
operation
operation
Rev.7.00 Mar. 18, 2009 page 557 of 1136
Section 11 16-Bit Timer Pulse Unit (TPU)
REJ09B0109-0700