HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 264
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Section 6 Bus Controller (BSC)
6.6.7
If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the T
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
frequency of this LSI. Figure 6.23 shows an example of the timing when the RAS signal goes low
from the beginning of the T
Rev.7.00 Mar. 18, 2009 page 196 of 1136
REJ09B0109-0700
Read
Write
Note: n = 2 to 5
Figure 6.23 Example of Access Timing when RAS Signal Goes Low from Beginning
Row Address Output State Control
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
r
state.
T
of T
p
Row address
r
State (CAST = 0)
T
r
High
High
T
c1
Column address
T
c2
r
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