HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 167

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Legend:
1:
0:
—: Retains value prior to execution.
(EXR) are saved in the stack.
from the vector table to the PC, and program execution starts from that address.
Interrupt Control Mode
Set to 1
Cleared to 0
Trap Instruction Exception Handling
Status of CCR and EXR after Trap Instruction Exception Handling
0
2
1
1
I
CCR
UI
⎯
⎯
Rev.7.00 Mar. 18, 2009 page 99 of 1136
Section 4 Exception Handling
I2 to I0
⎯
⎯
REJ09B0109-0700
EXR
⎯
T
0