HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 919

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address
Program Data Operation Chart
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison
4. A 128-byte areas for storing program data, reprogram data, and additional
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 26.1.6, Flash Memory Characteristics.
Original Data
written to must be H'00 or H'80. A 128-byte data transfer must be performed
even if writing fewer than 128 bytes; in this case, H'FF data must be written to
the extra addresses.
between stored data in the program data area and verify data). Programming is
executed for the bits of reprogram data 0 in the next reprogram loop. Even bits
for which programming has been completed will be subjected to additional
programming if they fail the subsequent verify operation.
program data must be provided in the RAM. The contents of the reprogram and
additional program data are modified as programming proceeds.
the programming operation. See Note 7 for the pulse widths. When writing
of additional-programming data is executed, a (z3) μs write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
Note 7: Write Pulse Width
Note: Use a z3 µs write pulse for additional
(D)
Number of Writes (n)
0
1
Reprogram data storage
Additional program data
storage area (128 bytes)
Write pulse application subroutine
Wait (z1) μs or (z2) ms or (z3) μs
Program data storage
area (128 bytes)
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
Set PSU bit in FLMCR1
Write pulse application
Clear P bit in FLMCR1
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
Verify Data
.
.
.
RAM
Disable WDT
Enable WDT
Wait (α) μs
Wait (β) μs
Wait (y) μs
(V)
End sub
0
1
0
1
Reprogram Data
Write Time (z) μs
(X)
1
0
1
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
Figure 20.7 Program/Program-Verify Flowchart
.
.
.
*6
*5 *6
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Comments
Increment address
Section 20 Flash Memory (0.35-μm F-ZTAT Version)
Store 128-byte program data in program
NG
data area consecutively to flash memory
additional program data area in RAM to
Additional Program Data Operation Chart
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
Reprogram Data
H'FF dummy write to verify address
Transfer additional program data to
data area and reprogram data area
Sequentially write 128-byte data in
Reprogram data computation
additional program data area
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
(additional programming)
(X')
Write pulse application
Set PV bit in FLMCR1
Write pulse application
Start of programming
0
1
End of programming
Write data = verify
Read verify data
(z1) μs or (z2) μs
data verification
flash memory
Wait (x) μs
Wait (ε) μs
completed?
Wait (γ) μs
Wait (η) μs
Wait (θ) μs
data area
128-byte
m = 0?
m = 0
6 ≥ n ?
6 ≥ n ?
(z3) µs
data?
n = 1
Start
Rev.7.00 Mar. 18, 2009 page 851 of 1136
Verify Data
OK
OK
OK
OK
OK
(V)
Sub-routine-call
Subroutine-call
0
1
0
1
NG
NG
NG
Additional Program Data
NG
*6
*6
*4
*1
See Note 7 for pulse width
*6
*2
*4
*3
*4
*6
*1
*6
(Y)
0
1
m = 1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE bit in FLMCR1
Programming failure
Wait (θ) μs
n ≥ (N)?
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
OK
*6
REJ09B0109-0700
Comments
NG
n ← n + 1
*6