HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 327

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access
is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI
bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance
with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show
examples of idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even
if bits ICIS1 and ICIS0 are set to 1.
UCAS, LCAS
Address bus
Data bus
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
RAS
Figure 6.76 Example of Idle Cycle Operation after DRAM Access
RD
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DRAM space read
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Idle cycle
External address space read
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Rev.7.00 Mar. 18, 2009 page 259 of 1136
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Section 6 Bus Controller (BSC)
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DRAM space read
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REJ09B0109-0700
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