HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 384

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
7.5.4
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
Rev.7.00 Mar. 18, 2009 page 316 of 1136
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and transfer destination
Set number of transfers
Repeat Mode
Set transfer source
Idle mode setting
Read DMABCRL
Set DMABCRH
Set DMABCRL
Set DMACR
addresses
Idle mode
Figure 7.6 Example of Idle Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address and transfer
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTE bit to 1 to enable transfer.
• Clear the FAE bit to 0 to select short address
• Specify enabling or disabling of internal
destination address in MAR and IOAR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
• Select the activation source with bits DTF3 to
• Set the DTIE bit to 1.
mode.
interrupt clearing with the DTA bit.
decremented with the DTID bit.
DTF0.
bit.