HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 469

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is
enabled, and byte-size, single address mode transfer (write) is performed from an external device
to external 8-bit, 2-state access space.
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
φ
Address bus
HWR
LWR
EDACK
ETEND
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Bus release
DMA write
Bus release
DMA write
Bus release
DMA write
Rev.7.00 Mar. 18, 2009 page 401 of 1136
Section 8 EXDMA Controller (EXDMAC)
Bus release
DMA write
transfer
cycle
Last
REJ09B0109-0700
Bus release

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