HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 477

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an
EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted.
The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For
external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA
cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.35 to 8.38 show operation timing examples for various conditions.
φ pin
EDREQ
EDRAK
Bus cycle
ETEND
EDA bit
Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode
1
Bus release
(No Contention/Dual Address Mode/Low Level Sensing)
EXDMA
read
EXDMA
write
Bus release
3 cycles
Rev.7.00 Mar. 18, 2009 page 409 of 1136
Section 8 EXDMA Controller (EXDMAC)
EXDMA
Last transfer cycle
read
EXDMA
write
REJ09B0109-0700
0
Bus release