HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 184

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 5 Interrupt Controller
5.3.5
ISR is an IRQ15 to IRQ0 interrupt request flag register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Note:
Rev.7.00 Mar. 18, 2009 page 116 of 1136
REJ09B0109-0700
Bit Name
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
* Only 0 can be written, to clear the flag.
IRQ Status Register (ISR)
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
Description
[Setting condition]
When the interrupt source selected by ISCR occurs
[Clearing conditions]
Cleared by reading IRQnF flag when IRQnF =
1, then writing 0 to IRQnF flag
When interrupt exception handling is executed
when low-level detection is set and IRQn input
is high
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the DTC
is cleared to 0
(n = 15 to 0)

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