HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 514

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Data Transfer Controller (DTC)
Table 9.7
Mode
Normal
Repeat
Block transfer
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 9.8
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev.7.00 Mar. 18, 2009 page 446 of 1136
REJ09B0109-0700
Bus width
Access states
Execution
status
Object to be Accessed
Number of execution states = I · S
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
Register Information
Read/Write
J
6
6
6
S
S
S
S
S
S
S
I
J
K
K
L
L
M
Chip
RAM
On-
32
—
1
1
1
1
1
1
I
+ Σ (J · S
ROM
Chip
On-
16
—
1
1
1
1
1
1
J
On-Chip I/O
+ K · S
Registers
—
—
2
8
2
4
2
4
Data Read
K
1
1
N
K
16
—
—
+ L · S
2
2
2
2
2
1
L
—
Data Write
L
1
1
N
) + M · S
2
4
2
4
2
4
External Devices
8
6+2m
6+2m
6+2m
3+m
3+m
—
3
M
Internal
Operations
M
3
3
3
—
2
2
2
2
2
2
16
3+m
3+m
3+m
3+m
3+m
—
3