HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 163

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Exception Source
External interrupt
Internal interrupt *
Notes: 1. Lower 16 bits of the address.
4.3
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 14,
Watchdog Timer (WDT).
The interrupt control mode is 0 immediately after reset.
4.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 4.1 and 4.2 show examples of the reset sequence.
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
2. Not available in this LSI.
3. Not available in this LSI. It is reserved for system use.
4. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Reset
Reset Exception Handling
Vector Table.
4
IRQ13
IRQ14
IRQ15
31
Vector Number
29
30
32
118
⎜
Normal Mode *
H'003A to H'003B
H'003C to H'003D
H'003E to H'003F
H'0040 to H'0041
H'00EC to H'00ED
Rev.7.00 Mar. 18, 2009 page 95 of 1136
⎜
Vector Address *
2
Section 4 Exception Handling
Advanced Mode
H'0074 to H'0077
H'0078 to H'007B
H'007C to H'007F
H'0080 to H'0083
H'01D8 to H'01DB
REJ09B0109-0700
1
⎜