HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 1176

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix
D.
Table D.1 shows the execution state of each instruction in this LSI.
[Explanation of Table Contents:]
[Legend:]
R:B
R:W
W:B
W:W
:M
2nd
3rd
4th
5th
NEXT
EA
VEC
Figure D.1 shows the timing of the address bus, RD, HWR, and LWR during execution of the
sample instruction above (example in "Explanation of Table Contents") with an 8-bit bus, 3-state
access, and no wait.
Rev.7.00 Mar. 18, 2009 page 1108 of 1136
REJ09B0109-0700
Instruction
Bus State during Execution of Instructions
R:W 2nd
1
Reading in bytes
Reading in words
Writing in bytes
Writing in words
Bus mastership cannot be handed over immediately after this cycle
Address of second word (3rd and 4th bytes)
Address of third word (5th and 6th bytes)
Address of fourth word (7th and 8th bytes)
Address of fifth word (9th and 10th bytes)
Start address of instruction immediately following the instruction being executed
Effective address
Vector address
1 state of inter-
nal operation
2
R:W EA
3
4
Order of execution
End of instruction
Read the effective address in words.
Read/write is not performed.
Read the second word of the instruction that is being executed in words.
5
6
7
8