HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 388

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 7 DMA Controller (DMAC)
7.5.5
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in single address mode.
Table 7.8
Register
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
Rev.7.00 Mar. 18, 2009 page 320 of 1136
REJ09B0109-0700
23
15
Single Address Mode
DACK pin
Register Functions in Single Address Mode
ETCR
MAR
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Write
strobe
Transfer counter
Function
Destination
address
register
Read
strobe
Start address of
transfer destination
or transfer source
(Set automatically
by SAE bit; IOAR is
invalid)
Number of transfers See sections 7.5.2,
Operation
See sections 7.5.2,
Sequential Mode,
7.5.3, Idle Mode, and
7.5.4, Repeat Mode.
Strobe for external
device
Sequential Mode,
7.5.3, Idle Mode, and
7.5.4, Repeat Mode.

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