ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 98

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

17.8.2
17.8.3
98
ATmega4HVD/8HVD
ADCL and ADCH – The ADC Data Register
DIDR0 – Digital Input Disable Register 0
Table 17-3.
When an ADC conversion is complete, the result is found in these two registers.When ADCL
is read, the ADC Data Register is not updated until ADCH is read.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
on page
• Bit 7:1 – RES: Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must always be written to zero when DIDR0 is written.
• Bit 0 – PB0DID: PB0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the Port B pin is disabled. The PIN
register bit will always read as zero when this bit is set. When an analog signal is applied to
the PB0 pin and the digital input from this pin is not needed, this bit should be written logic one
to reduce power consumption in the digital input buffer.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
96.
ADC Channel Input Selection
ADC7
15
R
R
R
7
0
–
7
0
0
-
ADMUX1:0
00
01
10
11
ADC6
14
R
R
R
6
0
–
6
0
0
-
ADC5
13
R
R
R
–
5
0
0
5
0
-
ADC4
12
R
R
R
–
4
0
0
4
0
-
ADC3
11
R
R
–
3
0
0
3
R
0
-
ADC2
10
R
R
–
2
0
0
R
2
0
-
Reserved
VTEMP
VCELL
ADC0
Input
”ADC Conversion Result”
ADC9
ADC1
R
R
9
1
0
0
R
1
0
-
PB0DID
ADC8
ADC0
R/W
R
R
8
0
0
0
0
0
8052B–AVR–09/08
ADCH
ADCL
DIDR0