ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 40

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

10.3
10.4
10.5
40
External Reset
Watchdog Reset
Black-out Detection
ATmega4HVD/8HVD
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see
reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage, V
delay counter starts the MCU after the timeout period, t
Figure 10-2. External Reset During Operation
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration.
On the falling edge of this pulse, the delay timer starts counting the timeout period t
to
Figure 10-3. Watchdog Reset During Operation
ATmega4HVD/8HVD has an on-chip Black-out Detection (BLOD) circuit for monitoring the
VREG level during operation by comparing it to a trigger level defined by hardware.
The ATmega4HVD/8HVD has two detection levels and two application areas for BLOD, see
”System and Reset Characteristics” on page
to ensure that the voltage on VFET is sufficient to operate the voltage regulator within its spec-
ifications when the chip starts up. The other detection level is used during normal operation
(V
BLOT, NORMAL
page 38
for details on operation of the Watchdog Timer.
FET
FET
) to determine if VREG drops below a voltage where correct operation cannot be
”System and Reset Characteristics” on page
CK
144. One detection level (V
TOUT
, has expired.
RST
, on its positive edge, the
BLOT, START-UP
144) will generate a
8052B–AVR–09/08
TOUT
) is used
. Refer