ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 124

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

23.5.5
124
ATmega4HVD/8HVD
Reading the Signature Row from Software
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing
instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-save sleep mode during periods of low V
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
tion is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear 6 cycles after writing to SPMCSR, which is locked for further writ-
ing during these cycles. The LPM instruction must be executed within 3 CPU cycles after
writing SPMCSR. When SIGRD and SPMEN are cleared, LPM will work as described in the
Instruction set Manual.
Table 23-1.
Signature Byte Description
Device ID 0, Manufacture ID
Device ID 1, Flash Size
Device ID 2, Device
FOSCCAL
FOSC SEGMENT
Reserved
SLOW RC Period L
SLOW RC Period H
SLOW RC Temp Prediction L
SLOW RC Temp Prediction H
SLOW RC FREQ
ULP RC FREQ
Reserved
Reserved
Batt Prot Adjust Factor
Reserved
VPTAT CAL L
VPTAT CAL H
The internal Black-out Detection circuit will issue an internal reset immediately and
take the chip in power-off after 4 CPU cycles if the operating voltage drops below the
detection level V
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
Table 23-1
(1)
(8)
Signature Row Addressing
(6)
(5)
(2)
(3)
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruc-
BLOD
(7)
. Alternatively, an external low V
(4)
CC
reset protection circuit can be
Z-Pointer Address
0FH:11H
0CH
0DH
08H
0BH
0AH
0EH
00H
02H
04H
01H
03H
05H
06H
07H
09H
12H
13H
CC
. This will pre-
8052B–AVR–09/08