ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 43

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

10.6.2
8052B–AVR–09/08
Start-up with two FETs connected
chip is powered and an internal Power-on Reset (POR) is generated. During the initial start-up
when a valid reference for the voltage regulator is missing, VCC is driven as close as possible
to VFET. Voltage regulation will only start when VCC has reached V
sents the voltage level that guarantees proper start-up conditions for the voltage regulator.
Even though the voltage regulator has started up and the digital part is powered, the chip is
kept in RESET state until VCC exceeds V
is met, BLOD will be released and the Reset Delay counter starts counting. VREG will now be
regulated to its nominal value. The Reset Delay counter makes sure that the chip is continu-
ously kept in RESET state internally for a time corresponding to the start-up time selected by
the SUT fuses (time indicated as t
quence of this start-up scheme, the start-up period must be measured from BLOD is released,
and not from the time that a charger is connected. The time from a charger is detected until
BLOD is released may be significant in the one-FET application if the V
mum and BLOD level is at its maximum.
During start-up VCC may exceed its nominal value of operation for a short time period. This
overshoot will typically occur when V
output follows VFET until the regulator enters normal mode. However, this situation will only
occur during start-up while the chip is kept in RESET state, and will not occur in normal
operation.
For two FET applications, the VFET node is high-impedant as long as C-FET is switched off.
This means that the VFET voltage and hence also the BATT voltages increase rapidly once a
charger is connected. The charger will be detected almost immediately and the voltage regula-
tor is switched on.
A typical start-up sequence for the application is illustrated in
TOUT
BLOT, START-UP
in
BLOT, start-up
Figure 10-8 on page
is at its maximum value since the regulator
. Once the condition VCC > V
ATmega4HVD/8HVD
Figure 10-9 on page
42). Note that as a conse-
BLOT, start-up
POT
level is at its mini-
, which repre-
44.
BLOT, start-up
43