ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 36

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

9.7.3
9.7.4
9.7.5
9.7.6
9.8
9.8.1
36
Register Description
ATmega4HVD/8HVD
On-chip Debug System
Battery Protection
ADC
FET Driver
SMCR – Sleep Mode Control Register
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep
modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse
should be disabled when debugWire is not used.
If one of the Battery Protection features is not needed by the application, this feature should be
disabled, see
sumption in the Battery Protection circuitry is only significant in Power-save mode. Disabling
both FETs will automatically disable the Battery Protection module in order to save power.
If enabled, the ADC will consume power independent of sleep mode. To save power, the ADC
should be disabled when not used, and before entering Power-save sleep mode. See
Analog-to-Digital Converter” on page 90
ADC0, the digital input buffer of this pin should be disabled by setting the PB0DID bit in the
DIDR0 register.
To minimize the power consumption in Power-save mode, the DUVR mode of the FET Driver
should be disabled to make sure that the Fast RC Oscillator is stopped.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega4HVD/8HVD, and will always read as zero.
• Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0
These bits select between the four available sleep modes as shown in
Table 9-3.
Bit
Read/Write
Initial Value
SM2
0
0
0
0
1
”BPCR – Battery Protection Control Register” on page
Sleep Mode Select
R
7
–
0
SM1
R
6
–
0
0
0
1
1
0
R
5
–
0
for details on ADC operation. When PB0 is used as
SM0
R
4
–
0
0
1
0
1
0
SM2
R/W
3
0
Sleep Mode
Idle
ADC Noise Reduction
Reserved
Power-save
Power-off
SM1
R/W
2
0
SM0
R/W
1
0
Table
109. The current con-
9-3.
R/W
SE
0
0
8052B–AVR–09/08
SMCR
”ADC -