ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 132

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

24.6.1
132
ATmega4HVD/8HVD
Serial Programming Algorithm
Table 24-8.
The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low: > 2.2 CPU clock cycles for f
High: > 2.2 CPU clock cycles for f
When writing serial data to the ATmega4HVD/8HVD, data is clocked on the rising edge of
SCK.
When reading data from the ATmega4HVD/8HVD, data is clocked on the falling edge of SCK.
See
To program and verify the ATmega4HVD/8HVD in the Serial Programming mode, the follow-
ing sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
Apply minimum 3V between VFET and GND, and BATT and GND while RESET and
SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is
held low during power-up. In this case, RESET must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte
must be loaded before data high byte is applied for a given address. The Program
memory Page is stored by loading the Write Program memory Page instruction with the
6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least
t
gramming interface before the Flash write operation completes can result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the 2 LSB of the address and data together with
the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored
by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the
Figure 26-1
WD_FLASH
Symbol
MISO
MOSI
SCK
before issuing the next page. (See
Pin Mapping Serial Programming
and
Figure 26-2
Pins
WD_EEPROM
PB1
PB2
PC1
for timing details.
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
before issuing the next byte. (See
I/O
O
I
I
Table
24-9.) Accessing the serial pro-
Table
Serial Data out
Serial Data in
Description
Serial Clock
ck
ck
>= 12 MHz
>= 12 MHz
24-10):
Table
8052B–AVR–09/08
24-9.) In