ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 72

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

15.4
15.5
15.5.1
72
External Clock Source
Register Description
ATmega4HVD/8HVD
TCCRnB – Timer/Counter n Control Register B
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The syn-
chronized (sampled) signal is then passed through the edge detector.
functional equivalent block diagram of the Tn synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects. See
Figure 15-2. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors)
tolerances, it is recommended that maximum frequency of an external clock source is less
than f
An external clock source can not be prescaled.
Note:
• Bits 2, 1, 0 – CSn2, CSn1, CSn0: Clock Select0, Bit 2, 1, and 0
The Clock Select n bits 2, 1, and 0 define the prescaling source of Timer n.
Bit
Read/Write
Initial Value
clk_I/O
Tn
The synchronization logic on the input pins (
clk
/2.5.
I/O
R
7
0
-
D
LE
Q
R
6
0
-
ExtClk
Synchronization
D
R
5
0
< f
-
Q
clk_I/O
Table 15-1 on page 73
/2) given a 50/50% duty cycle. Since the edge detector
R
T
4
0
-
n
pulse for each positive (CSn2:0 = 7) or negative
Tn)
R
3
0
-
is shown in
for details.
CSn2
R/W
D
2
0
Q
Figure
CSn1
R/W
15-2.
1
0
Edge Detector
Figure 15-2
clk
CSn0
I/O
R/W
0
0
). The latch is
8052B–AVR–09/08
Tn_sync
(To Clock
Select Logic)
shows a
TCCRnB
Tn
). The