ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 58

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

58
ATmega4HVD/8HVD
Figure 13-3. High Voltage Digital I/O
Note:
Table 13-1
Figure 13-3
internally in the modules having the alternate function.
Table 13-1.
Signal Name
PVOE
PVOV
DIEOE
DIEOV
DI
1. WRx, RRx and RPx are common to all pins within the same port. clk
mon to all ports. All other signals are unique for each pin.
summarizes the function of the overriding signals. The pin and port indexes from
are not shown in the succeeding tables. The overriding signals are generated
Generic Description of Overriding Signals for Alternate Functions
Pxn
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
Full Name
Port Value
Override Enable
Port Value
Override Value
Digital Input
Enable Override
Enable
Digital Input
Enable Override
Value
Digital Input
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
0
1
Description
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared,
and the Output Driver is enabled, the port Value is controlled
by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the schmitt trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use
its own synchronizer.
DIEOExn
DIEOVxn
(1)
SLEEP
1
0
SYNCHRONIZER
PVOExn
PVOVxn
D
L
SET
CLR
RRx:
WRx:
RPx:
clk
DIxn:
SLEEP:
Q
_
Q
I/O
:
D
PINxn
RESET
CLR
PORTxn
READ PORTx REGISTER
WRITE PORTx REGISTER
READ PINx REGISTER
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
SLEEP CONTROL
Q
Q
_
Q
Q
CLR
_
D
clk
RRx
RPx
WRx
I/O
DIxn
I/O
and SLEEP are com-
8052B–AVR–09/08