ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 34

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

9.2
9.3
9.4
34
Idle Mode
ADC Noise Reduction
Power-save Mode
ATmega4HVD/8HVD
Table 9-2.
Notes:
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing all peripheral functions to continue operating. This sleep
mode basically halts clk
enables the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow interrupt.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, Watchdog Timer (WDT), Cur-
rent Battery Protection (CBP), and the Ultra Low Power RC Oscillator (RCOSC_ULP) to
continue operating. This sleep mode basically halts clk
the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements.
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. In this mode, the internal Fast RC Oscillator (RCOSC_FAST) is stopped, while
Watchdog Timer (WDT), Current Battery Protection (CBP) and the Ultra Low Power RC Oscil-
lator (RCOSC_ULP) continue operating.
This mode will be the default mode when application software does not require operation of
CPU, Flash or any of the peripheral units running at the Fast internal Oscillator
(RCOSC_FAST).
Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-save mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined in
Module
VREG
CHARGER_DETECT
VREGMON
OSI
1. Discharge FET must be switched off for Charger Detect to be enabled.
2. RCOSC_FAST runs in Power-save mode if DUVR mode is enabled. It also runs for approxi-
3. Runs only when OSI is enabled and RCOSC_SLOW is selected as source for OSI.
mately 128 ms after C-FET/D-FET has been enabled.
Active modules in different Sleep Modes (Continued)
(1)
CPU
and clk
Active
X
X
X
X
FLASH
Idle
, while allowing the other clocks to run. Idle mode
X
X
X
X
ADC Noise
Reduction
X
X
X
I/O
”Clock Sources” on page
, clk
Mode
CPU
”External Interrupt” on page 53
, and clk
Power-save
X
X
FLASH
, while allowing
8052B–AVR–09/08
23.
Power-off
X