ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 54

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

12.1.2
12.1.3
54
ATmega4HVD/8HVD
EIMSK – External Interrupt Mask Register
EIFR – External Interrupt Register
be changed. Finally, the INTn interrupt flags should be cleared by writing a logical one to its
Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.
Table 12-1.
Note:
• Bits 7:2 – RES: Reserved Bits
These bits are reserved bits in the ATmega4HVD/8HVD, and will always read as zero.
• Bit 1:0 – INT1:0: External Interrupt Request 1:0 Enable
When the INT1 - INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in
the External Interrupt Control Register – EICRA – defines whether the external interrupt is acti-
vated on rising or falling edge or level sensed. Activity on this pin will trigger an interrupt
request even if the pin is enabled as an output. This provides a way of generating a software
interrupt.
• Bits 7:2 – RES: Reserved Bits
These bits are reserved bits ins the ATmega4HVD/8HVD, and will always read as zero.
• Bits 1:0 – INTF1:0: External Interrupt Flag 1:0
When an edge or logic change on the INT1:0 pin triggers an interrupt request, INTF1:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1:0 in
EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ISCn1
0
0
1
1
1. n = 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are
changed.
Interrupt Sense Control
ISCn0
R
R
7
–
0
7
–
0
0
1
0
1
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge of INTn generates an interrupt request.
The rising edge of INTn generates an interrupt request.
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
INTF1
INT1
R/W
R
1
0
1
0
INTF0
INT0
R/W
R
0
0
0
0
8052B–AVR–09/08
EIMSK
EIFR