ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 115

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

21.2
21.2.1
21.2.2
8052B–AVR–09/08
FET Driver
Features
Overview
•
•
The ATmega4HVD/8HVD includes a FET Driver. The FET Driver is designed for driving N-
channel FETs used as high side switch in 1-Cell Li-Ion battery pack. A block diagram of the
FET driver is shown in
When charging deeply over-discharged cells, the FET Driver will be operated in Deep Under-
Voltage Recovery (DUVR) mode. In DUVR mode the FET Driver regulates the voltage at the
VFET pin to typically 2.3 Volts in 1-Cell applications. This is done by operating the Charge
FET at a point where the drain-source voltage is equal to the voltage difference between the
cell voltage and the required VFET operating voltage. As the cell voltage increases, the drain-
source voltage of the Charge FET will decrease until the Charge FET is completely on. See
Table 26-6 on page 146
In normal operation (DUVRD = 1), the Charge FET/Discharge FET is switched on by pumping
OC/OD sufficiently above the VFET supply voltage. To turn off the Charge FET/Discharge
FET, OC/OD is pulled quickly low. See
for details..
Figure 21-2. FET Driver block diagram.
Charge-pump for generating suitable gate drive for N-Channel FET switch on high side
Deep Under-voltage Recovery mode that allows normal operation while charging a Deeply
Over-discharged battery from 0-volt
BANDGAP
CONTROL
_VREG
LDO
REF.
FET
CLK
Figure
for details.
DUVRD
CHARGE_EN
DISCHARGE_EN
CLK_OSC
DVDD
DUALC_MODE
VREF
21-2.
Figure 21-3 on page 116
Charge
C-FET
Pump
14V clamp
Charge FET
Charge
D-FET
1k
Pump
ATmega4HVD/8HVD
NFET DRIVER
Discharge FET
1k
14V clamp
and
Table 26-6 on page 146
BATT+
BATT-
115