ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 133

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

24.6.2
Table 24-10. Serial Programming Instruction Set
8052B–AVR–09/08
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Serial Programming Instruction set
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Table 24-9.
Table 24-10 on page 133
Symbol
t
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
WD_FUSE
address. When using EEPROM page access only byte locations loaded with the Load
EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY) is not used, the used must wait at least t
before issuing the next page (See
data file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
power off.
Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Byte 1
$AC
$AC
$4D
$C1
$A0
$F0
$48
$40
$28
$20
$58
$30
$50
$58
and
Figure 24-2 on page 135
Table
adr MSB
adr MSB
adr MSB
adr MSB
adr MSB
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$08
24-9). In a chip erased device, no 0xFF in the
Instruction Format
Minimum Wait Delay
ATmega4HVD/8HVD
describes the Instruction set.
Extended adr
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
adr LSB
4.5 ms
4.0 ms
4.0 ms
4.5 ms
Byte 3
$00
$00
$00
$00
$00
$00
high data byte out
low data byte out
high data byte in
low data byte in
WD_EEPROM
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
Byte4
$00
$00
$00
133