ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 79

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.6.1
8052B–AVR–09/08
Input Capture Trigger Source
Figure 16-4. Input Capture Unit Block Diagram
The Output Compare Register OCRnA is a dual-purpose register that is also used as an 8-bit
Input Capture Register ICRn. In 16-bit Input Capture mode the Output Compare Register
OCRnB serves as the high byte of the Input Capture Register ICRn. In 8-bit Input Capture
mode the Output Compare Register OCRnB is free to be used as a normal Output Compare
Register, but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there
are no free Output Compare Register(s). Even though the Input Capture register is called
ICRn in this section, it is referring to the Output Compare Register(s). For more information on
how to access the 16-bit registers refer to
When a change of the logic level (an event) occurs on the Input Capture pin (ICPx), and this
change confirms to the setting of the edge detector, a capture will be triggered. When a cap-
ture is triggered, the value of the counter (TCNTn) is written to the Input Capture Register
(ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is
copied into Input Capture Register. If enabled (TICIEn=1), the Input Capture Flag generates
an Input Capture interrupt. The ICFn flag is automatically cleared when the interrupt is exe-
cuted. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O
bit location.
The default trigger source for the Input Capture unit is the I/O port PC0 in Timer/Counter0 and
the Battery Protection Interrupt in Timer/Counter1. Alternatively can the osi_posedge pin on
the Oscillator Sampling Interface in Timer/Counter0 and Voltage Regulator Interrupt in
Timer/Counter1 be used as trigger sources. The osi_posedge pin in Timer/Counter0 Control
Register A (TCCR0A) and the Voltage Regulator Interrupt bit in the Timer/Counter1 Control
Register A (TCCR1A) is selected as trigger sources by setting the Input Capture Select
(ICS0/1) bit. Be aware that changing trigger source can trigger a capture. The Input Capture
Flag must therefore be cleared after the change.
Both Input Capture inputs are sampled using the same technique. The edge detector is also
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. An Input Capture on
Timer/Counter0 can also be triggered by software by controlling the port of the PC0 pin.
ICPn1
ICPn0
WRITE
OCRnB (8-bit)
TEMP (8-bit)
ICRn (16-bit Register)
OCRnA (8-bit)
ICSn
DATA BUS
”Accessing Registers in 16-bit Mode” on page
Canceler
Noise
ICNCn
(8-bit)
TCNTnH (8-bit)
ATmega4HVD/8HVD
TCNTn (16-bit Counter)
Detector
ICESn
Edge
TCNTnL (8-bit)
ICFn (Int.Req.)
82.
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