ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 57

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

13.1
13.1.1
13.1.2
13.2
8052B–AVR–09/08
High Voltage Ports as General Digital Outputs
Alternate Port Functions
Configuring the Pin
Reading the Pin
The high voltage ports are high voltage tolerant open collector output ports.
a functional description of one output port pin, here generically called Pxn.
Figure 13-2. General High Voltage Digital I/O
Note:
Each port pin consist of two register bits: PORTxn and PINxn. As shown in
tion” on page
at the PINx I/O address.
If PORTxn is written logic one, the port pin is driven low (zero). If PORTxn is written logic zero,
the port pin is tri-stated. The port pins are tri-stated when a reset condition becomes active,
even if no clocks are running.
The port pin can be read throughthe PINxn Register bit. As shown in
Register bit and the preceding latch constitute a synchronizer. This is needed to avoid meta-
stability if the physical pin changes value near the edge of the internal clock, but it also
introduces a delay.
The High Voltage I/O has an alternate port function in addition to being general digital I/O.
ure 13-3
overridden by alternate functions.
1. WRx, RRx and RPx are common to all pins within the same port. clk
shows how the port pin control signals from the simplified
mon to all ports.
Pxn
60, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits
SLEEP:
clkI/O:
SLEEP CONTROL
I/O CLOCK
SLEEP
(1)
SYNCHRONIZER
RRx:
WRx:
RPx:
D
L
RESET
CLR
SET
PORTxn
Q
Q
_
ATmega4HVD/8HVD
CLR
Q
Q
_
READ PORTx REGISTER
WRITE PORTx REGISTER
READ PINx REGISTER
D
D
PINxn
CLR
Q
_
Q
RRx
WRx
clk
RPx
Figure
I/O
I/O
Figure 13-2
and SLEEP are com-
Figure 13-2
”Register Descrip-
13-2, the PINxn
can be
shows
Fig-
57