ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 136
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ATMEGA8HVD-4MX
Manufacturer Part Number
ATMEGA8HVD-4MX
Description
MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8HVD-4MX.pdf
(168 pages)
Specifications of ATMEGA8HVD-4MX
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.4 V
Data Converters
A/D 1x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
18-MLF® Exposed Pad (Staggered Leads), DFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
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24.8
24.8.1
24.8.2
136
High-voltage Serial Programming Algorithm
ATmega4HVD/8HVD
Enter High-voltage Serial Programming Mode
Considerations for Efficient Programming
To program and verify the ATmega4HVD/8HVD in the High-voltage Serial Programming
mode, the following sequence is recommended (See instruction formats in
The following algorithm puts the device in (High-voltage) Serial Programming mode:
1. Set Prog_enable pins listed in
2. Apply 3.0 - 3.5V between V
3. Wait 20 - 60 µs, and apply V
4. Keep the Prog_enable pins unchanged for at least t
5. Release Prog_enable[1] pin to avoid drive contention on the Prog_enable[1]/SDO pin.
6. Wait at least 300 µs before giving any serial instructions on SDI/SII.
If the rise time of the V
tive algorithm can be used.
1. Set Prog_enable pins listed in
2. Apply 3.0 - 3.5V between V
3. Monitor V
4. Keep the Prog_enable pins unchanged for at least t
5. Release Prog_enable[1] pin to avoid drie contention on the Prog_enable[1]/SDO pin.
6. Wait until V
Table 24-13. High-voltage Reset Characteristics
The loaded command and address are retained in the device during programming. For effi-
cient programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory
• Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the
• Address High byte needs only be loaded before programming or reading a new 256 word
locations.
EESAVE Fuse is programmed) and Flash after a Chip Erase.
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
Supply Voltage
and V
reaches at least 1.8V within the next 20 µs.
been applied to ensure the Prog_enable Signature has been latched.
V
been applied to ensure the Prog_enable Signature has been latched.
SDI/SII.
CC
3.0V
3.5V
V
to 0V. VFET should not be connected.
CC
CC
to 0V. VFET should not be connected.
CC
CC
, and as soon as V
actually reaches 3.0 - 3.5V before giving any serial instructions on
RESET Pin High-voltage Threshold
CC
is unable to fulfill the requirements listed above, the following alterna-
CC
CC
HRST
and GND, and between BATT and GND. Ensure that V
and GND, and between BATT and GND.
Table 24-12 on page 135
Table 24-12 on page 135
CC
V
11.5V
11.5V
HVRST
- 12.5V to RESET.
reaches 0.9 - 1.1V, apply V
HVRST
HVRST
Minimum High-voltage Period for
to “0000”, RESET pin to 0V
to “0000”, RESET pin to 0V,
after the High-voltage has
after the High-voltage has
HRST
Latching Prog_enable
- 12.5V to RESET.
t
10 µs
10 µs
HVRST
Table
8052B–AVR–09/08
24-14):
CC
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